what kind of wafers are used at intel to make computer chips

For the variety of food, run into Wafer.

Sparse slice of semiconductor used for the fabrication of integrated circuits

Top: polished 12" and 6" silicon wafers. Their crystallographic orientation is marked by notches and apartment cuts (left). VLSI microcircuits made on a 12-inch (300 mm) silicon wafer, before dicing and packaging (right). Bottom: solar wafers on the conveyor (left) and completed solar wafer (right)

In electronics, a wafer (besides called a piece or substrate)^[1] is a thin piece of semiconductor, such equally a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells. The wafer serves as the substrate for microelectronic devices built in and upon the wafer. It undergoes many microfabrication processes, such as doping, ion implantation, carving, sparse-pic degradation of diverse materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and packaged as an integrated excursion.

History [edit]

This section needs expansion. You lot can assist by adding to it. (January 2015)

In the semiconductor or silicon wafer industry, the term wafer appeared in the 1950s to describe a thin round slice of semiconductor textile, typically germanium or silicon. Round shape comes from single-crystal ingots usually produced using the Czochralski method. Silicon wafers were outset introduced in the 1940s.^{[two] [3]}

Past 1960, silicon wafers were being manufactured in the U.S. past companies such as MEMC/SunEdison. In 1965, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley, while working under IBM, filed Patent US3423629A^[4] for the first loftier-chapters epitaxial apparatus.

Silicon wafers are fabricated by companies such as Sumco, Shin-Etsu Chemical,^[5] Hemlock Semiconductor Corporation and Siltronic.

Production [edit]

Germination [edit]

Wafers are formed of highly pure,^{[half dozen]} about defect-gratuitous single crystalline material, with a purity of 99.9999999% (9N) or higher.^[6] One process for forming crystalline wafers is known as the Czochralski method, invented past Smooth chemist January Czochralski. In this procedure, a cylindrical ingot of high purity monocrystalline semiconductor, such equally silicon or germanium, called a boule, is formed by pulling a seed crystal from a melt.^{[seven] [8]} Donor impurity atoms, such every bit boron or phosphorus in the instance of silicon, can exist added to the molten intrinsic cloth in precise amounts in social club to dope the crystal, thus changing it into an extrinsic semiconductor of north-type or p-type.

The boule is then sliced with a wafer saw (a blazon of wire saw), machined to meliorate flatness, chemically etched to remove crystal damage from machining steps and finally polished to course wafers.^[9] The size of wafers for photovoltaics is 100–200 mm square and the thickness is 100–500 μm.^[10] Electronics apply wafer sizes from 100 to 450 mm bore. The largest wafers fabricated take a bore of 450 mm,^[11] only are not yet in general use.

Cleaning, texturing and etching [edit]

Wafers are cleaned with weak acids to remove unwanted particles. There are several standard cleaning procedures to make sure the surface of a silicon wafer contains no contamination. 1 of the most constructive methods is RCA make clean. When used for solar cells, the wafers are textured to create a crude surface to increase surface area and then their efficiency. The generated PSG (phosphosilicate glass) is removed from the border of the wafer in the etching.^[12]

Wafer properties [edit]

Standard wafer sizes [edit]

Silicon [edit]

Silicon wafers are available in a multifariousness of diameters from 25.iv mm (1 inch) to 300 mm (11.8 inches).^{[xiii] [fourteen]} Semiconductor fabrication plants, colloquially known as fabs, are defined by the bore of wafers that they are tooled to produce. The bore has gradually increased to improve throughput and reduce price with the current country-of-the-fine art fab using 300 mm, with a proposal to adopt 450 mm.^{[15] [16]} Intel, TSMC and Samsung were separately conducting research to the advent of 450 mm "prototype" (inquiry) fabs, though serious hurdles remain.^[17]

2-inch (51 mm), four-inch (100 mm), 6-inch (150 mm), and viii-inch (200 mm) wafers

Wafer size	Typical thickness	Year introduced [13]	Weight per wafer	100 mm2 (ten mm) Die per wafer
one-inch (25 mm)		1960
2-inch (51 mm)	275 μm	1969		ix
three-inch (76 mm)	375 μm	1972		29
four-inch (100 mm)	525 μm	1976	10 grams [18]	56
4.ix inch (125 mm)	625 μm	1981		95
150 mm (5.nine inch, usually referred to equally "half-dozen inch")	675 μm	1983		144
200 mm (7.nine inch, usually referred to as "viii inch")	725 μm.	1992	53 grams [18]	269
300 mm (11.8 inch, normally referred to every bit "12 inch")	775 μm	2002	125 grams[eighteen]	640
450 mm (17.vii inch) (proposed)[19]	925 μm	–	342 grams [18]	1490
675-millimetre (26.6 in) (theoretical)[20]	unknown	–	unknown	3427

Wafers grown using materials other than silicon will take different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the cloth used; the wafer must exist thick enough to support its own weight without cracking during handling. The tabulated thicknesses relate to when that process was introduced, and are non necessarily correct currently, for example the IBM BiCMOS7WL process is on 8-inch wafers, simply these are simply 200 μm thick. The weight of the wafer goes up along with its thickness and diameter.^{[ citation needed ]}

Historical increases of wafer size [edit]

A unit of wafer fabrication step, such equally an etch step, can produce more fries proportional to the increase in wafer area, while the toll of the unit fabrication step goes upwardly more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from 200 mm wafers began in early on 2000, and reduced the price per die for about 30–40%.^[21] Larger bore wafers allow for more than dice per wafer.

Photovoltaic [edit]

This section needs expansion. Y'all tin can assist by adding to it. (July 2020)

M1 wafer size (156.75 mm) is in the process of beingness phased out in People's republic of china as of 2020. Various nonstandard wafer sizes have arisen, so efforts to fully adopt the M10 standard (182 mm) are ongoing. Like other semiconductor fabrication processes, driving downwardly costs has been the main driving cistron for this attempted size increase, in spite of the differences in the manufacturing processes of different types of devices.^{[ citation needed ]}

Crystalline orientation [edit]

Diamond cubic crystal structure of a silicon unit cell

Flats can be used to announce doping and crystallographic orientation. Red represents material that has been removed.

Wafers are grown from crystal having a regular crystal construction, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm).^[22] When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with (100) or (111) faces being the nigh common for silicon.^[22] Orientation is important since many of a unmarried crystal'south structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer'due south crystal orientation, since each direction offers distinct paths for transport.^[23]

Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows information technology to be easily diced into individual fries ("dies") then that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.^{[ citation needed ]}

Crystallographic orientation notches [edit]

Wafers under 200 mm diameter take flats cut into one or more sides indicating the crystallographic planes of the wafer (unremarkably a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (run across illustration for conventions). Wafers of 200 mm diameter and higher up utilize a unmarried small notch to convey wafer orientation, with no visual indication of doping type.^[24]

Impurity doping [edit]

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 10^thirteen and 10¹⁶ atoms per cm³ of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer equally either bulk north-type or p-type.^[25] However, compared with single-crystal silicon's atomic density of v×10²² atoms per cm³, this still gives a purity greater than 99.9999%. The wafers can also exist initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum.^[26] Transition metals, in particular, must be kept beneath parts per billion concentrations for electronic applications.^[27]

450 mm wafers [edit]

Challenges [edit]

At that place is considerable resistance to the 450 mm transition despite the possible productivity improvement, because of concern about insufficient return on investment.^[21] There are as well issues related to increased inter-die / edge-to-edge wafer variation and boosted edge defects. 450mm wafers are expected to cost iv times as much as 300mm wafers, and equipment costs are expected to ascension past 20 to l%.^[28] College price semiconductor fabrication equipment for larger wafers increases the cost of 450 mm fabs (semiconductor fabrication facilities or factories). Lithographer Chris Mack claimed in 2012 that the overall price per dice for 450 mm wafers would be reduced by only 10–20% compared to 300 mm wafers, because over 50% of full wafer processing costs are lithography-related. Converting to larger 450 mm wafers would reduce price per die only for process operations such equally compose where price is related to wafer count, not wafer area.^{[ commendation needed ]} Toll for processes such as lithography is proportional to wafer area, and larger wafers would not reduce the lithography contribution to die cost.^[29]

Nikon planned to deliver 450-mm lithography equipment in 2015, with volume production in 2017.^{[30] [31]} In November 2013 ASML paused development of 450-mm lithography equipment, citing uncertain timing of chipmaker demand.^[32]

In 2012, a grouping consisting of New York State (SUNY Poly/College of Nanoscale Science and Engineering (CNSE)), Intel, TSMC, Samsung, IBM, Globalfoundries and Nikon companies has formed a public-individual partnership called Global 450mm Consortium (G450C, similar to SEMATECH) who made a v-yr plan (expiring in 2016) to develop a "cost constructive wafer fabrication infrastructure, equipment prototypes and tools to enable coordinated industry transition to 450mm wafer level".^{[33] [34]} In the mid of 2014 CNSE has appear that it will reveal first fully patterned 450mm wafers at SEMICON West.^[35] In early 2017 the G450C began to dismantle its activities over 450mm wafer inquiry due to undisclosed reasons.^{[36] [37] [38]} Diverse sources have speculated that demise of the group came after charges of bid rigging fabricated against Alain East. Kaloyeros, who at the time was a chief executive at the SUNY Poly.^{[38] [37] [39]} The industry realization of the fact that the 300mm manufacturing optimization is more than inexpensive than costly 450mm transition may besides accept played a function.^[38]

The timeline for 450 mm has not been fixed. In 2012, information technology was expected that 450mm production would start in 2017, which never realized.^{[xl] [41]} Mark Durcan, and then CEO of Micron Engineering, said in February 2014 that he expects 450 mm adoption to be delayed indefinitely or discontinued. "I am not convinced that 450mm volition ever happen simply, to the extent that it does, information technology's a long fashion out in the future. There is not a lot of necessity for Micron, at least over the next five years, to be spending a lot of money on 450mm."^[42]

At that place is a lot of investment that needs to go on in the equipment community to make that happen. And the value at the finish of the day – so that customers would buy that equipment – I recall is dubious."^[43] Equally of March 2014, Intel Corporation expected 450 mm deployment past 2020 (by the finish of this decade).^[44] Mark LaPedus of semiengineering.com reported in mid-2014 that chipmakers had delayed adoption of 450 mm "for the foreseeable futurity." Co-ordinate to this written report some observers expected 2018 to 2020, while G. Dan Hutcheson, chief executive of VLSI Enquiry, didn't meet 450mm fabs moving into production until 2020 to 2025.^[45]

The step up to 300 mm required major changes, with fully automated factories using 300 mm wafers versus barely automatic factories for the 200 mm wafers, partly because a FOUP for 300 mm wafers weighs about vii.5 kilograms^[46] when loaded with 25 300 mm wafers where a SMIF weighs about 4.viii kilograms^{[47] [48] [18]} when loaded with 25 200 mm wafers, thus requiring twice the amount of concrete forcefulness from factory workers, and increasing fatigue. 300mm FOUPs have handles and then that they can exist still be moved past manus. 450mm FOUPs weigh 45 kilograms^[49] when loaded with 25 450 mm wafers, thus cranes are necessary to manually handle the FOUPs^[50] and handles are no longer nowadays in the FOUP. FOUPs are moved effectually using material handling systems from Muratec or Daifuku. These major investments were undertaken in the economical downturn post-obit the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe. On the ramp-up to 450 mm, the crystal ingots will be three times heavier (total weight a metric ton) and take 2–4 times longer to cool, and the procedure time will be double.^[51] All told, the development of 450 mm wafers requires significant engineering, fourth dimension, and cost to overcome.

Analytical die count estimation [edit]

In guild to minimize the toll per dice, manufacturers wish to maximize the number of dies that can be fabricated from a single wafer; dies e'er have a square or rectangular shape due to the constraint of wafer dicing. In full general, this is a computationally complex trouble with no analytical solution, dependent on both the area of the dies as well equally their aspect ratio (square or rectangular) and other considerations such every bit the width of the scribeline or saw lane, and additional space occupied past alignment and test structures. Notation that gross DPW formulas account only for wafer area that is lost because it cannot be used to brand physically consummate dies; gross DPW calculations exercise not business relationship for yield loss due to defects or parametric issues.^{[ citation needed ]}

Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer.

Nevertheless, the number of gross die per wafer (DPW) tin be estimated starting with the first-order approximation or floor part of wafer-to-die area ratio,

${\displaystyle DPW=\left\lfloor {\frac {\pi r^{two}}{S}}\right\rfloor =\left\lfloor {\frac {\pi d^{2}}{4S}}\right\rfloor }$ ,

where

This formula simply states that the number of dies which can fit on the wafer cannot exceed the area of the wafer divided by the area of each individual die. Information technology volition e'er overestimate the true best-case gross DPW, since information technology includes the area of partially patterned dies which do not fully prevarication on the wafer surface (see figure). These partially patterned dies don't correspond consummate ICs, so they cannot be sold as functional parts.^{[ commendation needed ]}

Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general volition be more meaning when the area of the dice is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible.^{[ citation needed ]}

The correction factor or correction term generally takes one of the forms cited by De Vries:^[52]

${\displaystyle DPW={\frac {\displaystyle \pi d^{two}}{4S}}-{\frac {\displaystyle \pi d}{\sqrt {2S}}}}$ (expanse ratio – circumference/(die diagonal length))

or ${\displaystyle DPW=\left({\frac {\displaystyle \pi d^{ii}}{4S}}\right)\exp(-two{\sqrt {Due south}}/d)}$ (area ratio scaled by an exponential cistron)

or ${\displaystyle DPW={\frac {\displaystyle \pi d^{2}}{4S}}\left(1-{\frac {\displaystyle 2{\sqrt {S}}}{d}}\right)^{2}}$ (area ratio scaled past a polynomial factor).

Studies comparing these analytical formulas to brute-strength computational results show that the formulas can exist made more than accurate, over practical ranges of die sizes and aspect ratios, past adjusting the coefficients of the corrections to values higher up or below unity, and by replacing the linear die dimension ${\displaystyle {\sqrt {Due south}}}$ with ${\displaystyle (H+W)/2}$ (boilerplate side length) in the case of dies with large aspect ratio:^[52]

${\displaystyle DPW={\frac {\displaystyle \pi d^{ii}}{4S}}-0.58^{*}{\frac {\displaystyle \pi d}{\sqrt {Due south}}}}$

or ${\displaystyle DPW=\left({\frac {\displaystyle \pi d^{2}}{4S}}\right)\exp(-two.32^{*}{\sqrt {South}}/d)}$

or ${\displaystyle DPW={\frac {\displaystyle \pi d^{2}}{4S}}\left(ane-{\frac {\displaystyle 1.16^{*}{\sqrt {Southward}}}{d}}\correct)^{2}}$ .

Compound semiconductors [edit]

While silicon is the prevalent cloth for wafers used in the electronics industry, other chemical compound 3-Five or 2-VI materials take also been employed. Gallium arsenide (GaAs), a III-V semiconductor produced via the Czochralski method, gallium nitride (GaN) and silicon carbide (SiC) are too common wafer materials, with GaN and sapphire existence extensively used in LED manufacturing.^[8]

Run into besides [edit]

• Die preparation
• Epitaxial wafer
• Epitaxy
• Klaiber's law
• Monocrystalline silicon
• Polycrystalline silicon
• Rapid thermal processing
• RCA clean
• SEMI font
• Silicon on insulator (SOI) wafers
• Solar cell
• Solar panel
• Wafer bonding

References [edit]

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External links [edit]

Wikimedia Commons has media related to Wafers.

• Evolution of the Silicon Wafer by F450C -An infographic about the history of the silicon wafer.

jenkinsonthandeant.blogspot.com

Source: https://en.wikipedia.org/wiki/Wafer_%28electronics%29

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